Pull-Down Resistor Calculator – Sizing, Logic Levels & Standard Values

Hold a Signal LOW When Nothing Drives It

V_cc Supply Voltage

V_IL Max Input LOW Voltage

R_drv Driver Output Resistance (optional — for precise sizing)

Pull-Down Resistor Result

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Pull-Down Resistor
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E24 standard value

Max R_pd

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for valid LOW

Voltage at Pin

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Sink Current (idle)

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Current When HIGH

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V_cc / R_pd

Power Dissipation

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Pull-Down Resistor Circuit

A pull-down resistor connects the signal line to GND, holding the input LOW when no driver is active. Without it, a floating input picks up noise and toggles unpredictably.

R_drv — Driver output resistance. When the driver is off/tri-state, R_pd pulls the line LOW.
R_pd — Pull-down resistor. Connects signal to GND. Must be low enough to keep V_low below V_IL.
V_IL — Maximum input LOW voltage threshold. The pin reads LOW if voltage is below this.
V_low — Actual voltage at the junction. Must be ≤ V_IL for a valid logic LOW.

Pull-Down Resistor Calculator

A pull-down resistor connects a signal line to ground (GND), ensuring the input reads a definite LOW when no active driver is present. Without it, a floating input picks up noise and oscillates unpredictably between HIGH and LOW — causing false triggers, erratic behaviour, and intermittent faults that are notoriously difficult to debug.

What Is a Pull-Down Resistor?

A resistor connected between a signal line and GND. When no driver is active, the resistor pulls the voltage down to 0 V (ground). When a driver outputs HIGH, current flows through the pull-down to ground — this is wasted power, but the signal reads HIGH correctly because the driver’s output impedance is much lower than the pull-down resistance. The pull-down is the complement of a pull-up resistor, which connects to Vcc instead of GND.

The Formula

R_max = V_IL / I_leak — maximum resistance from leakage

V_IL = maximum input LOW voltage (from IC datasheet)
I_leak = input leakage current (from IC datasheet)

I_HIGH = Vcc / R — current wasted when signal is driven HIGH
P_HIGH = Vcc² / R — power dissipated when HIGH

The leakage current through the pull-down creates a small voltage (V = I_leak × R). This voltage must stay below V_IL or the input may read as HIGH instead of LOW. Lower resistance gives better noise margin but wastes more current when the line is driven HIGH.

Pull-Down vs Pull-Up

Pull-Down — connects to GND. Default state = LOW. Used with active-HIGH signals, push-button switches to GND detection, MOSFET gate hold-off, and enable pins that should default to disabled.

Pull-Up — connects to Vcc. Default state = HIGH. Used with open-drain/open-collector outputs, I²C bus, active-LOW reset lines, and enable pins that should default to enabled.

The design process is identical — the same trade-offs between noise margin, current draw, and switching speed apply. The only difference is the direction: pull-down to GND, pull-up to Vcc.

3.3V CMOS Logic

3.3 V supply, V_IL = 0.8 V, I_leak = 1 µA.

R_max = 0.8 V / 1 µA = 800 kΩ

Recommended: 10 kΩ (E24 standard)
V_low = 1 µA × 10 kΩ = 10 mV (well below 0.8 V)
Noise margin = 0.8 V − 0.01 V = 790 mV

When HIGH: I = 3.3 V / 10 kΩ = 330 µA
Power: P = 3.3² / 10k = 1.09 mW

10 kΩ gives 790 mV of noise margin — excellent. The 330 µA current when HIGH is negligible for most circuits. For battery-powered designs where even 330 µA matters, 100 kΩ still gives 790 mV margin (V_low = 0.1 V) at only 33 µA. For finding the current through any resistor from first principles, see the Ohm’s Law Calculator.

5V TTL Logic

5 V supply, V_IL = 0.8 V (TTL standard), I_leak = 1 µA.

R_max = 0.8 V / 1 µA = 800 kΩ

Recommended: 10 kΩ
V_low = 10 mV, Margin = 790 mV

When HIGH: I = 5 V / 10 kΩ = 500 µA
Power: P = 5² / 10k = 2.5 mW

Same 10 kΩ works. The higher Vcc means slightly more current when HIGH (500 µA vs 330 µA), but still well within acceptable limits. TTL inputs have V_IL = 0.8 V regardless of whether the supply is 5 V or 3.3 V — always check the datasheet rather than assuming.

MOSFET Gate Pull-Down

12 V gate drive, V_GS(th) = 2.0 V (used as V_IL), I_leak = 10 µA.

R_max = 2.0 V / 10 µA = 200 kΩ

Recommended: 10 kΩ
V_low = 10 µA × 10 kΩ = 100 mV (well below 2 V threshold)
Noise margin = 1.9 V

When HIGH: I = 12 V / 10 kΩ = 1.2 mA
Power: P = 12² / 10k = 14.4 mW

This is critical for power MOSFETs. If the gate floats, the MOSFET may partially turn on — conducting uncontrolled current through the load, generating heat, and potentially destroying the MOSFET or the load. The 10 kΩ pull-down ensures the gate stays at 100 mV (firmly off) until the driver deliberately turns it on. For MOSFET gate drive design, see the MOSFET Gate Resistor Calculator.

Choosing the Right Value

1 kΩ — Strong pull-down. Best noise immunity. High current when HIGH (3.3 mA at 3.3 V). Use for noisy environments, long PCB traces, or high-speed signals.

10 kΩ — Standard default. Good balance of noise margin and current draw. Works for most digital logic applications.

100 kΩ — Weak pull-down. Minimal current draw (33 µA at 3.3 V). Good for battery-powered devices where every microamp counts. Vulnerable to noise pickup on long wires.

>100 kΩ — Very weak. Only for ultra-low-power sleep modes or where leakage is extremely low. Not recommended for general use — too sensitive to noise and parasitic capacitance slows response.

Common Applications

Push-Button Default LOW

A button connects the signal to Vcc when pressed. The pull-down holds the signal LOW when the button is released. Without it, releasing the button leaves the input floating. 10 kΩ is the standard choice for buttons — fast enough for human input, low enough current draw to ignore.

MOSFET Gate Hold-Off

Power MOSFETs must have their gate held LOW during power-up and when the controller is in reset. A 10 kΩ pull-down ensures the gate stays below V_GS(th) until the driver actively turns it on. Without this, the gate charges from parasitic capacitance coupling and the MOSFET turns on uncontrollably.

Enable Pin Default Disabled

Many IC enable pins are active-HIGH. A pull-down on the enable pin ensures the IC stays disabled until the controller deliberately enables it. This prevents the IC from activating during power-up sequencing before the controller is ready.

Bus Idle State

Some communication buses need a defined idle state. A pull-down on a data line defines idle as LOW, preventing bus contention and false start conditions when no device is transmitting.

Frequently Asked Questions

What is the standard pull-down resistor value?

10 kΩ is the most common default for digital logic. It works well with 3.3 V and 5 V CMOS, gives good noise margin, and draws minimal current. Use 1 kΩ for noisy environments or 100 kΩ for ultra-low-power designs.

What happens without a pull-down resistor?

The input floats. A floating CMOS input picks up electromagnetic noise and oscillates between HIGH and LOW unpredictably. This causes false triggers, increased power consumption (the input buffer sits in its linear region, drawing shoot-through current), and erratic system behaviour.

Can I use the MCU’s internal pull-down instead?

Yes, if your MCU has configurable internal pull-downs. Most ARM Cortex-M microcontrollers offer 20–50 kΩ internal pull-downs. They save a component but are weaker than external resistors — fine for low-noise PCB traces, not for long wires or noisy environments. They also are not active during reset, so the pin floats briefly at power-up.

When should I use a pull-down vs a pull-up?

Use a pull-down when the default state should be LOW (active-HIGH signals, MOSFET gates, enable pins that default to off). Use a pull-up when the default state should be HIGH (active-LOW resets, open-drain buses like I²C, enable pins that default to on).

Does the pull-down affect signal speed?

Yes. The pull-down and the parasitic capacitance of the signal line form an RC time constant. A 10 kΩ pull-down with 10 pF of trace capacitance: τ = 100 ns. The signal takes about 5τ = 500 ns to fully settle LOW. For high-speed signals, use a lower resistance (1 kΩ gives 50 ns) at the cost of more current when HIGH.

Why does my MOSFET turn on when I remove the gate driver?

The gate is floating. Parasitic capacitance (C_gd, Miller capacitance) couples drain voltage transients onto the gate, charging it above V_GS(th). A 10 kΩ pull-down to source prevents this by keeping the gate discharged. For high-side MOSFETs or fast switching, use 1–4.7 kΩ.

Last updated: March 2026